Could I have layout data of Eval-ADuM4070EBZ ?
UG403 Fig-13 and 14 is difficult to see details.
Moto-san: Here attached is zip file of the Gerbers. The Vias may seem small, but can be increased without a problem.
It is important to have short, wide traces for X1, X2 since they are primary switching nodes, where high peak currents occur. Schottky diodes are best for the secondary side, and ceramic capacitors are best for bypassing, with values of 10uF on the input and 47uF on the output recommended.
Attached are the Top and Bottom Layers saved as .JPG files.
Sorry for slow response.
Thank you very much for your support.
Your picture is clear and it looks same layout as Fig 1.
It is helpful for us.
Could I have VIA data or Gerber data?
Why are these through hall VIAs very small ?
Is it no good to use big through hall VIAs?
Could I have tips about layout ?
Thank you very much for your good support.
This is what I want to see.
X1,X2 lines might be going below -0.5, so it might need to put schottkys between X1,2 and GND1?
(It might depend on the layout)
and "Through hole fill" VIAs are better?
Moto: The designer and I do not see a need for the schottky diodes, since we don't see the negative voltages that need clamping.
The through hole fill you show could be used for high power applications, but may not be needed for the ADuM4070 applications.
Both the schottky diodes and through hole fill techniques could be used if needed.
I saw X1/2 terminals were negative-swing on Evaluation board, even probe ground line minimized
So it needs schottkys, I think.
Is it strange?
About VIAs, ADuM4070 evaluation board uses “through hole fill”.
So I asked.
Through hole OK, I understood.
Thank you very much
Retrieving data ...