I have a question about tABDD on ADAU1977.
The ADAU1977 data sheet table 6 on p.8 says that the tABDD(SDATAOUTx delay from BCLK falling) is 18 ns at maximum.
The Figure 2. Serial Output Port Timing on p.9 shows tABDD in Left justified mode, I2S mode, and Right justified mode.
In my case this time, I am using 24.576MHz crystal so one BCLK would be about 40 ns.
18ns (or less) of tABDD is only for Left justified mode?
I am asking this because the tABDD on I2S mode on figure 2 is about 40 ns.