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BF518 SPI interface

Question asked by AlexeyADI on Jun 17, 2011
Latest reply on Jun 17, 2011 by Prashant

Hardware Reference  Revision 1.0, September 2010 page 718, figure 17-1 on SPI block diagram  it’s stated that SPI has Four-deep FIFO before SPI_TDBR transmit register. It was decided to write in to SPI_TDBR all 4 words without reading status register:


*pSPI0_TDBR = 0x2F00;// switch on "1"
  *pSPI0_TDBR = 0x2E01;//switch off "0"


But this code doesn’t work properly.


It works only like that :


*pSPI0_TDBR = 0x2F00;// switch on "1"
       while(*pSPI0_STAT & (1<<3))
  *pSPI0_TDBR = 0x2E01;//switch off "0"


Therefor until the moment when TXS bit  in status register will be cleared it won’t be possible to transmit data.  Why is it be like this?