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SHARC 21489 - SPORT to SPDIF problem

Question asked by koty0f on Dec 22, 2015
Latest reply on Jan 13, 2016 by PrasanthR

Hello,

 

Im struggeling with SPDIF transmitter on 21489. There is SPORT0 which contains 4 mono transmit channels. I want to configure SPDIF on SPORT0_DA_O. I doublechecked frequencies looked for some emaples for 214xx procesors and still notnihg. When the clock is set as it is below in code DAI_04 isn't any signal. When I set DIT_HFCLK_I to lower frequency. Lets say 6 MHz it "starts" to work but data seems demaged.

 

I attach the code which may be useful.

 

 

 

 

/////////////////////////////////////////////////////////////////////////////////////

// initSPORT

/////////////////////////////////////////////////////////////////////////////////////

// SPORT Tx DMA source buffers

section("seg_dmda") int TxBlock_A0[NUM_SAMPLES*NUM_TX_SLOTS];

section("seg_dmda") int TxBlock_A1[sizeof(TxBlock_A0)];

section("seg_dmda") int TxBlock_B0[NUM_SAMPLES*NUM_TX_SLOTS];

section("seg_dmda") int TxBlock_B1[sizeof(TxBlock_B0)];

 

 

int TCB_TxBlock_A0[4] = { 0, sizeof(TxBlock_A0), 1, 0};

int TCB_TxBlock_A1[4] = { 0, sizeof(TxBlock_A0), 1, 0};

int TCB_TxBlock_B0[4] = { 0, sizeof(TxBlock_B0), 1, 0};

int TCB_TxBlock_B1[4] = { 0, sizeof(TxBlock_B0), 1, 0};

 

 

//Proceed from Block A0 to Block A1

TCB_TxBlock_A0[0] = (unsigned int) TCB_TxBlock_A1 + 3 - OFFSET ;

TCB_TxBlock_A0[3] = (int) TxBlock_A0 - OFFSET ;

//Proceed from Block A1 to Block A0

TCB_TxBlock_A1[0] = (unsigned int) TCB_TxBlock_A0 + 3 - OFFSET ;

TCB_TxBlock_A1[3] = (int) TxBlock_A1 - OFFSET ;

//Proceed from Block B0 to Block B1

TCB_TxBlock_B0[0] = (unsigned int) TCB_TxBlock_B1 + 3 - OFFSET ;

TCB_TxBlock_B0[3] = (int) TxBlock_B0 - OFFSET ;

//Proceed from Block B1 to Block B0

TCB_TxBlock_B1[0] = (unsigned int) TCB_TxBlock_B0 + 3 - OFFSET ;

TCB_TxBlock_B1[3] = (int) TxBlock_B1 - OFFSET ;

 

 

 

 

 

 

/////////////////////////////////////////////////////////////////////////////////////

// SPORT0 for transmit signal to DAC and mirror for SPDIF

/////////////////////////////////////////////////////////////////////////////////////

 

 

// External clock and frame syncs generated by PCG

  *pDIV0 = 0x00000000;  // Transmitter (SPORT0)

 

 

 

// Enabling DMA Chaining for SPORT0 TX

// Block 1 will be filled first

 

 

*pCPSP0A = (unsigned int)TCB_TxBlock_A0 - OFFSET + 3 + PCI;

*pCPSP0B = (unsigned int)TCB_TxBlock_B0 - OFFSET + 3 + PCI;

 

 

// sport0 control register set up as a transmitter in I2S mode */

// sport 0 control register, SPCTL0 = 0x000C01F0 */

*pSPCTL0 = SCHEN_A | SDEN_A | SCHEN_B | SDEN_B | SPTRAN | SLEN24 | OPMODE | SPEN_A | SPEN_B;

 

 

// sport0 receive multichannel companding enable registers

// no companding for 8 TX active timeslots

// no companding on SPORT0 transmit

*pMT0CCS0 = 0;

 

 

 

 

 

 

 

 

 

 

//////////////////////////////////////////////////////////////////////////////////////////////////

// configuration of PCGs and SRU section

//////////////////////////////////////////////////////////////////////////////////////////////////

 

 

*pPCG_CTLA1 = 8 | CLKASOURCE | FSASOURCE; // External FS A Source External CLK A Source

*pPCG_CTLA0 = 512 | ENFSA | ENCLKA; // CLK - 3,03 MHz ; FS - 48 kHz

*pPCG_CTLC1 = 2 | CLKCSOURCE | FSCSOURCE; // External FS A Source External CLK A Source

*pPCG_CTLC0 = 512 | ENFSC | ENCLKC; // CLK - 12,5 MHz ; FS - 48 kHz

 

 

// DAI_PB20_O - 25 MHz

SRU(DAI_PB20_O, PCG_EXTA_I);   // DAIP 20 to PCGA

SRU(HIGH, PBEN09_I);

SRU(PCG_CLKA_O, DAI_PB09_I);   // DAIP 09 to PCGA CLK

SRU(HIGH, PBEN01_I);

SRU(PCG_FSA_O, DAI_PB01_I);   // DAIP 01 to PCGA FS

 

 

SRU(DAI_PB20_O, PCG_EXTC_I);   // DAIP 20 to PCGA

 

 

SRU(DAI_PB09_O, SPORT0_CLK_I);   // DAIP 9 to SPORT0 CLK (CLK)

SRU(DAI_PB01_O, SPORT0_FS_I);    // DAIP 1 to SPORT0 FS (FS)

 

 

SRU(HIGH, PBEN04_I);

SRU(PCG_CLKA_O, DIT_CLK_I); //set to SPDIF clock 3,03 MHz

SRU(PCG_FSA_O, DIT_FS_I); //set to SPDIF frame sync 48 kHz

SRU(PCG_CLKC_O, DIT_HFCLK_I); //set to SPDIF high frequency clock 12,5 MHz

SRU(SPORT0_DA_O, DIT_DAT_I); //set to SPDIF dataA

 

 

SRU(DIT_O, DAI_PB04_I); //set SPDIF output to ADI_P4

 

 

 

 

 

 

 

 

/////////////////////////////////////////////////////////////////////////////////////////////////////

// SPDIF configuration

////////////////////////////////////////////////////////////////////////////////////////////////////

*pDITCTL = (DIT_EN|DIT_IN_I2S);

 

 

// SPDIF Setup code goes here

// Use default setting of SPDIF

*pDIRCTL=0x0;

 

 

 

Thanks for any advice

 

 

Filip Kotocek

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