I am using a custom board having adv7842 decoder on it, I have configured it in sdp mode and the video standard 720*480i/576i mode for cvbs input, and i have detect the video input by reading SDP_STD register which is giving PAL-BGHID input detected and by reading 0th bit of SDP_VIDEO_DETECTED register I can make sure valid video input detected.Decoder is configured 8 bit SDR mode but when i am trying to read the pixel port data using chipscope I am not getting proper video data I am getting some constatnt sequence of vlaue 80 05 80 8d as mentioned in attached image.
Please tell me where I am going wrong with my register setting.I am also unable to found the SAV EAV on chipscope. And HSYNC is generating at regular interval of 1728.We could see the transition of VSYNC also.
Register dump file can be found in attachment.
Thanks & Regards