I am using four AD7691 in "CS MODE, 4-WIRE WITHOUT BUSY INDICATOR", as explained on page 20 in the datasheet.
I have problems with the SDO (data output) that should be in high impedance mode, if SDI (used as Chip Select) is high (not selected). Quite often, after reading data from two of the four ADCs, the SDO is still not in high impedance mode, even though SDI is high on both chips. This means that the two other ADCs cannot be read correctly.
I have worked with this problem for hours, capturing all the relevant signals on my oscilloscope. It seems to me that the only way to make sure that SDO is in high-impedance mode is to set CNV low and then strobe SDI (set low, then high). This does not solve the problem, since the ADCs then loose their sample value.
The datasheet says "After the 18 th SCK falling edge, or when SDI goes high, whichever occurs first, SDO returns to high impedance and another AD7691 can be read." which I find is not entirely true.
So, my questions is: Why does the state of SDO (high-Z, low-Z) depend on other signals than SDI? And how can I make sure that SDO is in high-Z mode without setting CNV low?
Thank you in advance :-)