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BF547 EPPI latency

Question asked by erra on Jun 17, 2011
Latest reply on Jul 21, 2011 by WassimB



In the hardware reference page 15.4 it says:

When using an external EPPIx_CLK, there may be up to two cycles latency before valid data is received or transmitted.


We are using EPPI0 with an external clock in GP1 FS RX 16 bit mode, clock is 75MHz and supplied all the time.

FS1 is input.

Will there be a latency with invalid data in this case?

Are those samples zero or random value?

Is it random if it will be 0, 1 or 2 invalid samples in each RX buffer/line?