AnsweredAssumed Answered

Use L2 SRAM and data cache

Question asked by blueskull on Dec 18, 2015
Latest reply on Mar 29, 2016 by SachinV

Hi,

 

I'm now working on a project involves 48kpts of fract32, which is 192kB. Apparently, this is too big to be placed in L1 SRAM (32K+8K), so I need to put it into L2 SRAM. When I do nothing but declare a huge array, the DSP will simply hang up and lock itself.

 

So here is the question: How to declare an array in L2 SRAM?

 

With array declared in L2, it takes 2 cycles for the CPU to access it, which is not acceptable. So, how can I enable auto caching on this array so cache controller will automatically copy a portion of it at a time to L1, and access it from L1? I tried to enable allow data cache in .svc, and the DSP simply hangs itself up before even executing anything.

 

Therefore, here is the second question: How to enable data cache?

 

Forgive me if the questions are stupid, but I am a completely new player in DSP, and the only info regarding to cache is EE271, which is written for VDSP, while I am using CCES. FYI, my CCES version is 2.1.0.0 and my board is the $69 lite ez-kit with Rev. 1.0 chip.

 

 

 

 

Thanks,

Bo Gao

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