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AD9625 occasional invalid samples on JESD204B link

Question asked by tddo on Dec 17, 2015
Latest reply on Dec 24, 2015 by tddo

I'm currently working on a custom FPGA board using Altera Stratix V (GS) connected to three AD9625 ADCs, 2.6G version but configured for 2GSps operation.  For two of the ADCs, I got occasional period in which the sample data coming out of the Altera JESD204B IP core will all go to 0.  This happened for 52 samples and then valid samples appeared back (although not continuation of previous valid sample). Since we only used N=12-bit resolution with padded four bit (N’=16), when I set the padded four bits to be a LFSR instead of 0, the samples received would still occasionally go to 0 like before but the padded four bits continued to update even during the invalid samples. I suspect that there is a problem in the sample or frame construction in the ADC chip.  I wonder if anyone has seen this problem before with this chip.  Here is the information for my system

 

JESD204B generic 8 lanes mode

Subclass 0

L = 8

M = 1

F = 1

N = 12

N’ = 16

S = 4

K = 32

FC = 500MHz

Sampling rate  = 2Gsps

Scrambler enabled

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