I read the AD7760 datasheet and would like to verify my understanding, which is not clearly illustrate in the data sheet.
As define in Figure 3 of AD7760 data sheet which shows the register write process. Where Control Register 1 define in Table 15 allow to set 'RD STAT' bit for reading the contents of the status register as defined in Table 17.
So the timing diagram to complete the write and read process should be PIC1 or PIC2 or both is wrong?
PIC1: do not wait for DRDY pin go low and read the D[0-16] after WR pin go low.
PIC2: wait for DRDY pin go low, then pull the WR pin low and read the following D[0-16] which represent the Status register contents
Hope someone can clarify my doubt as described on above.