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AD9361:  FB_CLK in TDD mode

Question asked by kishore@stee.stengg.com on Dec 16, 2015
Latest reply on Mar 10, 2016 by tlili

Hi,

I have few questions related to  synchronizing clocks.

 

  • It was mentioned in reference manual that FB_CLK is a loop back version of the DATA_Clk but in TDD mode, receive section will be sleep mode so there won't be DATA_CLK going into the BB processor. Is this valid in LVDS mode as well???

 

  • How the below clocks are derived in AD9361 and which document should i refer to get more details. 

            ADC sampling frequency,DATA_CLK,RX_FRAME,FB_CLK and TX_frame.

FB_CLK.PNG


Thanks.

Regards,

Kishore.

 

 

 

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