Dear Community,

this is a call for help on a topic, that while it has been discussed before is of relevance for me.

As of lately I have been developing a circuit around the ADAU1701 in the scope of my bachelor thesis. When determining passive component values peripheral to the DSP I came across a formula for the resistor on ADC_RES in the datasheet:

These calculations of resistor values assume a 48 kHz sample

rate. The recommended input and current setting resistors

scale linearly with the sample rate because the ADCs have a

switched-capacitor input. The total value (2 kΩ internal plus

external resistor) of the ADC_RES resistor with sample rate

f S_NEW can be calculated as follows:

R_total = 20kR x 48000/f_s_NEW

Seeking for the best possible performance at minimal analog filter complexity I went for the all out approach, set the sampling frequency for the maximum 192kHz, and calculated the ADC_RES accordingly.

However now the ADC did not function at all and after some research here on the forums, this thread helped me a great deal in making the ADC work.

What I've come to understandso far ist that for the **native sample rates**, multiples of 48kHz, the resistor **MUST NOT** be changed. The register setting for 192kHz simply scales the oversampling factor to keep the delta-sigma modulator conversion frequency the same.

However now I wonder:

1. What is the oversampling factor (e.g. for the standard 48kHz sampling frequency) of the ADAU1701s ADC and DAC?

2. Why is the conversion rate of the sigma-delta modulator not stated in the datasheet, is it secret for a specific reason?

3. What is the advantage of using a sample frequency of greater than 48kHz if by increasing it the oversampling factor decreases?

Answers to any of these questions would be greatly appreciated.

MikeFoxtrot

Here's a non-official response (I don't work for ADI):

1 & 2) Probably because it's not that relevant for the end-user (converters haven't been marketed based on their oversampling rate for a while now), but most modern converters sample at 6.144MHz (for 48kHz), so that makes 128x at single-speed. Improvements in converters since the late '90s have come from multi-bit sampling rather than further increasing sample rate. So if you look around at other converter datasheets, you might not find that information there either.

3) Because you gain bandwidth, and thus maybe slightly flatter audio band (20kHz) performance due to the higher transition band, and maybe reducing aliasing for the same reason (sometimes transition bands maybe aren't as tight as you'd like if you are fastidious). Some applications might need 40kHz or 80kHz bandwidth.

If you don't need that bandwidth, then in theory and sometimes in practice, single-speed sample rates are probably better as they can have better dynamic range. If you look up some datasheets for really high-horsepower ADCs, you might find they specify lesser dynamic range at double-speed rates, and even less at quad-speed. Dan Lavry wrote a well-known whitepaper on this topic; you can search for it and it should pop up.

Of course, you lose precious instructions on -1701 if you run at double-speed.

But as much as I love -1701, its 100dBA converters aren't exactly top range, so I doubt much of this would be a concern. Use the sample rate you need for your project and don't worry about it.