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About register configuration sequence of ADAU1977(ADC)

Question asked by IRON on Dec 16, 2015
Latest reply on Jan 14, 2016 by DaveThib

Hello all,

I am now trying to accomplish a talk through program using ADAU1977(ADC), ADSP21489(DSP), and AD1934(DAC).

I have a question about register configuration of the ADC.

I am configuring ADC registers in the order below.


PLL_CONTROL        0x51

BST_CONTROL        0x4a



SAI_CTRL0              0x14

SAI_CTRL1              0x08

SAI_CMAP12            0x10

SAI_CMAP34       0x32                  

SAI_OVERTEMP        0xf8

POSTADC_GAIN1      0xa0

POSTADC_GAIN2      0xa0

POSTADC_GAIN3      0xa0

POSTADC_GAIN4      0xa0

M_POWER        0x01


Looking at the ADC’s data sheet p.37, there is a line saying

“The power management control register is used for enabling boost regulator, microphone bias, PLL, band gap reference, ADC, and LDO regulator.”

I understand that configuring this M_POWER register enables PLL according to this line.

A few days ago, I have gotten an answer from ADI “After locking PLL, I can freely configure any registers in any order.”

This M_POWER register is a register that I have to configure at the very first so that the PLL will be enabled?

Could you tell me the exact timing of M_POWER register configuration please?


Best Regards,

Yuta Mihara