AnsweredAssumed Answered

AD9361 Digital Interface Timing problem

Question asked by 85083074@qq.com on Dec 16, 2015
Latest reply on Dec 18, 2015 by DragosB

Hi,

     I am using FMCOMMS3 and ML605 FPGA for my design, And I have downloaded reference design(including HDL design and No -os).In the axi_ad9361 ip core,I find these files:

2.jpg

     I want to  transplant these out of the microblaze arm core(because I want to send and receive my own data),so I only transplant the axi_ad9361 and axi_ad9361_dev_if files.I don't know what  the other files' funciton   is. Are the others verilog programs only working for determine the TX/RX delay value?

     Then I use the default parameters to setup the ad9361. In the console, I saw

3.jpg

Tuning RX/TX failed!!!!  (Even using all original design,I also saw it failed,why?)


Is it meaning that I have a wrong Digital Interface Timing? What should I do with  Digital Interface Timing Verification [Analog Devices Wiki]

   Yours,

Wang

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