I need clarification on synchronizing Multiple AD9122 devices while using the PLL to multiply to a higher frequency. Looking at discussions
199965, 200548, and 211981 it is implied that you do not have to drive the DACCLK pins when using the internal clock multiplier, and that it will remain synchronized indefinitely after I reset the FIFO once with the PLL enabled.
Therefor the REFCLK is the sync clock and the multiplied REFCLK becomes the DACCLK. So you need to leave the DACCLK pins open, and just drive REFCLK.
However according to the datasheet on Page 52 it says.
Procedure for Synchronization When Using the PLL
In the initialization of the AD9122, all the clock signals (DACCLK, DCI, FRAME, synchronization, and REFCLK) must be present and stable before the synchronization feature is turned on.
So can you answer the following:
1 . In byte interface mode, FRAME is used to distinguish I and Q data. For synchronization, an extended duration FRAME is used to reset/align the internal FIFO. How does the extended duration FRAME signal interact with I/Q data framing? Can the sync FRAME function be performed during normal data transmission?
2. In internal PLL mode, REFCLK skew between the two parts must be less than half the multiplied up DACCLK period to maintain synchronization. Is this correct?
3. We do not need to drive DACCLK if we are using the PLL. All datasheet references to “DACCLK” refer to the internal node shown in the Figure 2 block diagram. So when the datasheet states that DACCLK must be present prior to synchronization, it means that (for the internal PLL case) REFCLK must be present and the PLL must be configured, selected, and locked?
Can you clarify this?