I have a question.
Could you explain the detailed function of the register bit "LR_POR"?
This register is just a register to invert LRCLK?
I am confused at the way the data sheet explain saying "lo then hi/ hi then lo"
I have been having a lot of trouble trying to understand exactly what you are saying. In figure 28 we do not say anything about the LR_POL bit setting. It needs to be set to 0 because in pulse mode the start of the frame will be a low to high LR clock transition. The LR_MODE bit needs to be set to "1" to set it up for pulse mode. That is shown in the diagram in figure 28. The other think is that figure 28 also shows several different variations of the data format, LJ, I2S TDM etc. So that added to the confusion.
One other thing that might help. In Table 30, the LR_POL bit description is describing an edge of the waveform. So Low to high is where the low-->high transition will mark the start of the frame. Then the clock will stay high for one BCLK cycle then it will go down for the rest of the frame.
But all these bits will still be valid even though you are in slave mode. You just need to match the settings to the actual LRCLK format that the SHARC is sending.
One other question, I think you are running the PLL using MCLK as an input correct? Because if you want to drive the PLL with a pulse LRCLK waveform then that is not a good idea.
I hope this helps.
I think you meant to type LR_POL.
Yes, this sets the polarity of the LR clock.
The low to high and high to low is in the context of the name of this bit which is LeftRight_Polarity. So you say left first then right. So the LRCLK will be low for the left channel and then high for the right.
If you set the bit to "1" then it will be High for the left channel and low for the right.
In TDM mode then it will start the frame low for one BCLK cycle then go high. when the bit is set to "0".
When it is set to "1" then it will be high at the start of the frame and then go low for the rest. This is shown in Figure 28.
So this is the reason for the language of High to low and low to high. So it will cover both usages, I2S and TDM.
Thank you for your answer.
As you may have already known, the LRCLK I am talking about here is the LRCLK which is being generated from the DSP(clock master ADSP21489).
What is the result of providing the clock source from the DSP when writing this bit" LR_POL"
The ADC would possibly work in a different way?
If you are using I2S then all it is going to do is swap the left and right channels when you change the polarity.
If you are using TDM and have the LRCLK format to 50/50 duty cycle then it will swap the first half of the channels with the second half. So for TDM 8 you would swap channels 1-4 with 5-8.
If you are using TDM in pulse mode then the data will start transmitting out on the falling edge of the LRCLK but that will be at the beginning of the pulse rather than the end of the pulse. This is the only situation where you could run into issues other than channels being swapped around.
Thank you so much for your answer.
I have a further question on this.
I am using TDM in pulse mode and I would like to get the LRCLK wave form just like fig.28 on the ADAU1977 data sheet p.26.
To acquire the shape, I have to set(=1) the LR_POR bit on Table 30. Bit Descriptions for BLOCK_POWER_SAI on the ADAU1977 data sheet p.41. That's what the data sheet say.
However, the desirable wave form will appear when I clear this bit.
I am now figuring out why this is happening.
A possible causation that I was thinking of on this matter is that I provide LRCLK from the Master SHARC.
In my system the ADC(ADAU1977) is a slave. Does it make any sense to configure the LR_POL bit when the ADC is a slave?
I totally understand about this matter.
I am so sorry for my misunderstanding.
Below is how I misunderstood this bit (LR_POL) configuration.
If I set the LR_POL bit, it would be "LRCLK High then Low".
When I looked at the figure.28, I thought the LRCLK waveform is being "High(for the 1BCLK length ) then low(for the rest of the frame)" but it is low then high. This was my misunderstanding.
High then low/ low then high are just talking about the transition.
Also Thank you so much for telling me how to use the LRCLK in Pulse mode by setting the bit "LR_MODE".
This also help me stop misunderstanding this point.
I understand that you had a logical interpretation of the datasheet text. I can see how you could come up with that. I think the text should have been "low to high edge" or "low to high transition". This way a person would not think it means the LRCLK is low first, for one BCLK period, then high for the rest of the frame.
Thanks for bringing this up.
I feel so happy for making this clear over 1 month misunderstanding.
This is all thanks to your diligent support.
I really appreciate that.
I should have used my imagination more too.
That would be great idea if the data sheet says "edge or transition" specifically.
This is just a reminder of this query.
I still need to get the answer for this.
I know you all are busy on this time of the year.
I am hoping to get the answer when you could.
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