AnsweredAssumed Answered

AD9361

Question asked by amboyle on Dec 15, 2015
Latest reply on Jan 11, 2016 by tlili

Hi tlli,

 

I had a conference call with the customer and they had more questions from your responses, I found some answers on the forum and reference manual, but there are some questions I could not find answers to. Can you help me out? They are the questions below that show" submitted to Analog devices, awaiting response. Also, I included all the questions with my answers, if I am incorrect please correct/comment where necessary.

 

  1. 1) Development Kits - comparison

          Sent recommendations and board comparisons in previous email.

  1. 2) Given the divider ratios of the RFPLL, What is the minimum and maximum size step that can be generated in the band 1-6GHZ. Also, do you have a configuration tool for the PLL?

          Submitted to Analog Devices, awaiting response.

  1. 3) Initialization and Calibration

Please see Initialization Calibrations page 7 of the AD9361 Reference manual. This chapter  It says…“Initialization calibrations are calibrations that must be run each time the AD9361 device is powered up or hard reset using the RESETB pin. Several of the calibrations only need to run once during initialization and do not re-run during operation. Others are dependent on the carrier frequency, temperature, or other parameters and need to run initially and when certain events occur (such as changing the carrier frequency more than 100 MHz). As long as power is applied to the AD9361 device, the calibration results are stored, including while in the SLEEP state.”

  1. 4) When switching Frequencies, does the AD9361 need to be re-calibrated?

I found the following response on the Analog Devices forum regarding AD9361 Frequency Switching Time, I pasted the below recommendations on changing frequency and locking PLL’s, however you can find the full question/answer at this link which goes into great detail on .               https://ez.analog.com/message/200921#200921 “The main variables for changing frequency and locking PLLs are reference clock frequency, mode of operation (TDD or FDD) and frequency change magnitude (greater than 100MHz change or less than 100MHz). Register map document provides a table with some typical times for frequency switching. Also, there are a number of posts on this forum that go in some detail on the topic.With a frequency change greater than 100MHz a number of calibrations need to be re-run. The documentation explains which calibrations need to run again. In addition to changing the frequency you need to change the bandwidth too. The time to do this will depend on the number of SPI writes required and SPI clock speed you are running in your system….” …… For example in TDD mode with 40MHz reference clock frequency the synthesizer will calibrate in 43us and lock in about 20us.  In FDD mode with 40MHz reference clock frequency the synthesizer will calibrate in 244.8us and lock in about 20us. There is a Fast Lock mode available that stores PLL settings in 8 different profiles. In this mode frequency change is reduced down to just the lock time of about 20us….

  1. 5)      Gain Control

Please see section on Gain Control, page 35 of the AD9361 Reference manual, Here is an excerpt from the section:“The AD9361 transceiver has several gain control modes that enable its use in a variety of applications. Fully automatic gain control (AGC) modes are available that address time division duplex (TDD) as well as frequency division duplex (FDD) scenarios. In addition, the AD9361 has manual gain control (MGC) options that allow the BBP to control the gain of the receiver. The ad9361_set_rx_gain_control_mode function configures all of the gain control modes.”

  1. 6) How do we calibrate the ADC over temperature range -20 Celcius to 85 Celcius

This is from Main PLL Block, page 17 of AD9361 Reference manualConfiguration for a given frequency consists of a combination of calculating the required divider values and referring to an Analog Devices supplied lookup table to configure the VCO for stable performance over temperature. The main PLL output is divided by the VCO divider block to create the frequency bands that allow the device to operate continuously from 70 MHz to 6 GHz.”The Synthesizer Look up Table is page 19 of AD9361 Reference Manual

  1. 7) What is the phase accuracy across the entire phase range? There are typically problems at 90 degrees and 180 degrees, and no issues at 45 degrees. i.e. there are usually problems in multiples of 90 degrees.

Submitted to Analog Devices, awaiting response.

  1. 8) What is the phase error at 60 db?

Submitted to Analog devices, awaiting response.

  1. 9) Is the ADC dynamic range of 60db the converter dynamic range?

**** When you say dynamic range, are you referring to signal to noise ratio of ADC?  ****

  1. 10) Does the internal ADC change the phase shift of the signal, if so, please explain.

Submitted to Analog Devices, awaiting response.

  1. 11) Is there any hardware changes required to cover the full frequency band 1GHz-6GHz?

Submitted to Analog Devices, awaiting response.

Outcomes