AnsweredAssumed Answered

Lane setup jesd204 for the HDL ad6676-ebz

Question asked by bhatnagar.vaibhav81 on Dec 15, 2015
Latest reply on Jan 12, 2016 by rejeesh

Hello,

 

I am using ad6676-ebz with zc706 using hdl rev 2015_r1, and noOS 2015_r1 (vivado 2014.4.1)

I have tested the logic on platform and found that it works well for default parameters (250MHz IF freq, 75MHz B.W., 3200GBPS fadc, dec 16, jesd204rx/tx 4gbps per lane) and 2 lanes of jesd204. It works good on the platform and we receive good samples.

 

Now I would like to configure jesd204 for 1 lane only. I tried to do it by soft by changing the setup parameters (lane and decimation) in ad6676_ebz.c as follows :

 

ad6676_init_param default_init_param = {

  200000000UL, // reference_clk_rate

  0, // spi_3_wire

  3200000000UL, // adc_frequency_hz

  250000000UL, // intermediate_frequency_hz

  MIN_FIF, // intermediate_frequency_min_hz

  MAX_FIF, // intermediate_frequency_max_hz

  75000000UL, // bandwidth_hz

  5, // bandwidth_margin_low_mhz

  5, // bandwidth_margin_high_mhz

  0, // bandwidth_margin_if_mhz

  32, // decimation

  19, // external_inductance_l_nh

  64, // idac1_fullscale_adjust

  0, // use_external_clk_enable

  1, // adc_frequency_fixed_enable

  1, // jesd_scrambling_enable

  1, // jesd_use_lvds_syncb_enable

  0, // jesd_powerdown_sysref_enable

  1, // jesd_l_lanes

  16, // jesd_f_frames_per_multiframe

  1, // shuffler_control

  5, // shuffler_thresh

  GPIO_ADC_OEN, // gpio_adc_oen

  GPIO_ADC_SELA, // gpio_adc_sela

  GPIO_ADC_SELB, // gpio_adc_selb

  GPIO_ADC_S0, // gpio_adc_s0

  GPIO_ADC_S1, // gpio_adc_s1

  GPIO_ADC_RESETB, // gpio_adc_resetb

  GPIO_ADC_AGC1, // gpio_adc_agc1

  GPIO_ADC_AGC2, // gpio_adc_agc2

  GPIO_ADC_AGC3, // gpio_adc_agc3

  GPIO_ADC_AGC4, // gpio_adc_agc4

};

 

 

On the console it prints

 

AD6676 successfully initialized.

JESD204B GT RX 0 PLL is locked.

JESD204B GT TX 0 PLL is locked.

JESD204B GT successfully initialized.

JESD204B successfully initialized.

JESD204B GT RX CLK is enabled.

ADC Core successfully initialized.

 

But we receives only zeros from from ddr3.

My questions is that in order to adapt the system for single lane, do we need to modify the HDL logic for example jesd204b configuration by ip_wizard as well as jesd_gt ip?

 

Please let me know.

 

Thanks in advance.

 

BR./

 

Vaibhav

tuananhdrg

Outcomes