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ADV212 - Raw Video mode, timing clarification & register settings

Question asked by pault on Jun 17, 2011
Latest reply on Jun 28, 2011 by DaveD

Hi,

 

I'd be grateful for any advice folk may have re using the ADV212 in Raw Video Mode.

 

We've loaded AD's test software & have got JDATA working correctly, however with our "real" design, after trying many different ordered combinations of register settings we managed to get the SCOMM[0..3] lines to "loop" for ~640ms before stopping. During this we were getting ADV212 headers (but no data) & a body size of 0xFFFE1A96. Reading the software flag register (SWFLAG) gives 0x6002 (which we believe to be an overflow).

 

Our application is low frame rate, monochrome, ~768x525 pixels.

As we didn't have much spare IO on our FPGA, so Raw Video mode & JDATA mode seemed a good choice, albeit with some warnings from AD that using it would require careful design (detailed in a separate document, Raw Mode Considerations).

 

Our MCLK = 12MHz, VCLK = 24MHz, JCLK = 96MHz & HCLK = 48MHz (although we have tried MCLK = VCLK = 24MHz & also tried JCLK = HCLK = 48MHz).

We're powering the 1.5V core from an LDO with a capacity of 500mA & we're seeing no problems on this rail (where this power supply design was based on the data sheet max current of 320mA).

 

Seemingly contradictory information is causing us a few problems, namely.....

 

1. There are contradictory timing diagrams for raw pixel mode. Which is correct?...
current data sheet, p17, Fig 28   OR    Programming Guide, p40, Fig32
These documents define timing diagrams which are different.
2. There are contradictory settings for EDMOD, BUSMODE specified for raw pixel mode. Which is correct?...
Programming Guide, p41, Fig 34    OR    User Guide, p32, Table 11     OR    User Guide, p52, Table 52
eg prog guide sets up DMMOD0 - b100 (reserved) while user guide (& also the Errata document) specifies b011 (JDATA mode)
3. There are contradictory settings for VMODE specified for raw pixel mode. Which is correct?...
User Guide, p49, Table 44 (PRGRSV_SCN = 1 for non-interlaced video)   OR    Programming Guide, p41, Fig 34 (PRGRSV_SCN = 0 for non-interlaced video)

 

If anyone can help with the above or has a list of the required register settings to get raw pixel mode working I would be very grateful.

 

Regards,

PaulT

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