The output data rate, which is listed in the datasheet, is the rate at which valid conversions are available when continuous conversions are being performed on a single channel. When the user switches to another channel, additional time is required for the sigma delta modulator and digital filter to settle. The settling time associated with these converters is the time it takes the output data to reflect the input voltage following a channel change. To accurately reflect the analog input following a channel change, the digital filter must be flushed of all data pertaining to the previous analog input.

For the AD779x devices, it takes 2 conversion times to clear the filter due to chopping. Therefore, if the output data rate is 16.6 Hz, for example, the time required to generate a settled conversion after switching channels equals 1/(2 x 16.6 Hz).

When a channel change occurs, the digital filter and modulator are automatically reset, /DRDY goes high and will remain high until a settled conversion is available from the ‘new’ analog input channel. Therefore, following a channel change, /DRDY will remain high until the digital filter has calculated a settled conversion (i.e. it will remain high for two conversion cycles).

When a step change occurs (on the analog input channel being converted), the ADC is not reset. The ADC continues to output conversions and /DRDY continues to pulse when a conversion is available. However, the conversions will not be settled as the digital filter will require the complete settling time to generate a digital word relevant to the altered analog input. If the step change occurs at the beginning of a conversion cycle, the ADC will output a settled conversion teo conversion cycles after the step change. However, if the step change occurs asynchronously so that it occurs in the middle of a conversion, the ADC needs to complete the present conversion and then perform 2 more conversions to generate an output valid to the ‘new’ analog input. Therefore, it may take 3 conversion cycles from the instant at which the step change occurs to the instant at which a valid conversion is available.

In summary, the channel switching speed is one half the output data rate. Therefore, in switching applications, such as data acquisition systems, it is important to realise that the rate at whch conversions are available from each channel is two times less than the output data rate achieved when continuously sampling on a single channel.

With the AD7794 and AD7795, chopping can be disabled. With chopping disabled, the settling time equals the conversion time. So, the ADC operates as a zero latency ADC. Therefore, when switching between channels, a settled conversion is available at (1/output data rate) after the channel change.

The output data rate, which is listed in the datasheet, is the rate at which valid conversions are available when continuous conversions are being performed on a single channel. When the user switches to another channel, additional time is required for the sigma delta modulator and digital filter to settle. The settling time associated with these converters is the time it takes the output data to reflect the input voltage following a channel change. To accurately reflect the analog input following a channel change, the digital filter must be flushed of all data pertaining to the previous analog input.

For the AD779x devices, it takes 2 conversion times to clear the filter due to chopping. Therefore, if the output data rate is 16.6 Hz, for example, the time required to generate a settled conversion after switching channels equals 1/(2 x 16.6 Hz).

When a channel change occurs, the digital filter and modulator are automatically reset, /DRDY goes high and will remain high until a settled conversion is available from the ‘new’ analog input channel. Therefore, following a channel change, /DRDY will remain high until the digital filter has calculated a settled conversion (i.e. it will remain high for two conversion cycles).

When a step change occurs (on the analog input channel being converted), the ADC is not reset. The ADC continues to output conversions and /DRDY continues to pulse when a conversion is available. However, the conversions will not be settled as the digital filter will require the complete settling time to generate a digital word relevant to the altered analog input. If the step change occurs at the beginning of a conversion cycle, the ADC will output a settled conversion teo conversion cycles after the step change. However, if the step change occurs asynchronously so that it occurs in the middle of a conversion, the ADC needs to complete the present conversion and then perform 2 more conversions to generate an output valid to the ‘new’ analog input. Therefore, it may take 3 conversion cycles from the instant at which the step change occurs to the instant at which a valid conversion is available.

In summary, the channel switching speed is one half the output data rate. Therefore, in switching applications, such as data acquisition systems, it is important to realise that the rate at whch conversions are available from each channel is two times less than the output data rate achieved when continuously sampling on a single channel.

With the AD7794 and AD7795, chopping can be disabled. With chopping disabled, the settling time equals the conversion time. So, the ADC operates as a zero latency ADC. Therefore, when switching between channels, a settled conversion is available at (1/output data rate) after the channel change.