AnsweredAssumed Answered

Re: BF518F - BF506F SPI communication problem

Question asked by marco55 on Oct 26, 2015
Latest reply on Dec 14, 2015 by Prashant
Branched from an earlier discussion

Hello,

I reopen this thread because I still have problems with this SPI communication:

the configuration is as before

master:

SPI_CTL = 1F00

SPI_FLG = FF00

SPI_BAUD = 0004

slave:

SPI_CTL = 4F24

SPI_FLG = FF00

the system clock is 80MHz for BF518 (master) and 100MHz for BF506 (slave).

 

The problem is that sometimes I see that the master receive some incorrect data and I so I noticed that on the slave side I have TXE and RBSY simultaneously.

 

The slave with BF506 performs other tasks: I use the other SPI to manage serialized digital I/O and also I am using the ADC control module.

I think that there is some timing issue due to the presence of all these simultaneous tasks, since sometimens I also have problems with ADC that show incorrect data.

 

adi_int_SICSetIVG(ADI_INT_ACM, 7);//ACM

adi_int_SICSetIVG(ADI_INT_DMA6_SPI0, 8);//DMA6 (Spi0 Rx/Tx) - communication with BF518

adi_int_SICSetIVG(ADI_INT_DMA2_SPORT0_RX, 9);//SPORT0  - ACM

adi_int_SICSetIVG(ADI_INT_TIMER0, 10);//TIMER0 - general delay

adi_int_SICSetIVG(ADI_INT_DMA7_SPI1, 11);//DMA7 (Spi1 Rx/Tx) - serialized digital I/O

 

register_handler(ik_timer,CoreTimerIsr);//Core Timer

register_handler(ik_ivg7,AcmIsr);//ACM

register_handler(ik_ivg8,Spi0Isr);//DMA6 (Spi0 Rx/Tx) - communication with BF518

register_handler(ik_ivg9,Sport0RxIsr);//SPORT0  - ACM

register_handler(ik_ivg10, GenDelayISR);//TIMER0 - general delay

register_handler(ik_ivg11,Spi1Isr);//DMA7 (Spi1 Rx/Tx) - serialized digital I/O

 

Any suggestion?

thank you in advance

 

Marco

Outcomes