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Multicore (BF561) project structure and definition

Question asked by Yaniv.Sapir on Jun 16, 2011
Latest reply on Jun 25, 2011 by Yaniv.Sapir

I am making my first steps in dual-core programming. Trying to build a program written for single-core EZ-KITs (BF533/BF518) on a BF561 platform, it seems like the PLL does not fire an interrupt after setting the clock rates, so the processor is stuck in IDLE. Trying to understasnd what's going on I tried looking at an example project form VisualDSP - the:


\Blackfin\Examples\ADSP-BF561 EZ-KIT Lite\UART RS-232 HyperTerminal (C)



This project group includes 5 projects, in which 2 deal with the shared memory and are effectively empty. The main project is empty of code as well. Then, there are two library projects intended for Core A and Core B, which hold the actual program code. Examining the project definitions raises many questions. The first issues are:


1. How does the project know which library to map to each of the cores?

2. If the output of the two projects in CoreA.dlb and CoreB.dlb, how exactly are the p0.dxe and p1.dxe executables created? Where do they come from?

3. And, what happened to the UART_Terminal.dxe output file (there is none, although the main project is supposedly generating an exe of this name)?