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Modify PL section for Zed board

Question asked by rakeshm55 on Dec 9, 2015
Latest reply on Dec 9, 2015 by CsomI

Hi,

 

I am using AD-FMCOMMS3-EBZ + Zedboard combi for SDR app....

I am trying to incorporate some modulation  and demodulation scheme to PL section of Zedboard.

 

I started with the default Zedboard HDL design....analogdevicesinc/hdl at hdl_2014_r2 · GitHub

Vivado 2014.2

For simplicity I tried to modify the receive chain ... i detached util_adc_pack between axi_dmac (ad9361 adc_dma) and introduced a custom module to drive axi_dmac(adc_dma).....The module directly captured data from input side of util_adc_pack....

 

The custom module was designed using ad9361_clk.....I was able to built the design without any timing errors.....Once I tried to burn the design the default ILA started behaving strange .... Here it shows no data capture from AD9361.....

 

So secondly I tried to recapture the using signals and data fed to ILA capture (sys_wfifo out) (these signals are in 100Mhz clk) ..... I introduced a fifo and re clocked to ad9361_clk and supplied the inputs to my module..... here too after burning the design  no data capture from AD9361.....

 

Thirdly I clocked my module using 100Mhz and tried to capture data from sys_wfifo out .... now i could capture data faithfully but in 100MHz domain......

 

My ADC sampling rate was 1.536Mhz ...... ADC clock is constraint for 250MHz......

 

Am I doing something wrong here???? Why the adc capture halts once I introduce a module using AD9361_clk??

 

Is there any guidelines to modify the rx path and tx path of PL section ??

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