I'm collecting some problems with the AD7190 serial communication.
I use the 3-wire serial interface (SCLK, DIN, DOUT) with CS tied low. SCLK is 10 kHz and the sequence of events is described below:
1. I power up the board
2. I set both SCLK and DIN
3. I send a train of 40 SCLK pulses with DIN setted to perform a reset (I also tried to increment the number of SCLK pulses up to 48).
After this operation I cannot always find the same signal state, I have two different conditions:
-DOUT/RDY is a low signal with high pulses of 100 microseconds spaced by 20ms. Each time I see the high pulse a new data is available. Is it correct? I can leave the system in this condition for a lot of time (some minutes) and signal modifications doesn't occur.
-DOUT/RDY is as I described before only for 4 "conversions" (4 high pulses); after that I always read a low DOUT/RDY signal. Also in this condition I can leave the system for minutes without signal modifications.
Which is the correct signal timing diagram after the reset condition in 3-wire serial communication interface? Am I doing mistakes?
I would like to use the AD7190 in continuos conversion mode (the default after power up / reset) so after the reset I send 8 SCLK pulses and h58 on DIN (rising edge synchronuos); than 2ms with DIN and SCLK tied high and after that a train of 24 SCLK pulses to read the data register. May be for reset mismatch but I cannot always see the same result on DOUT, also writing for example h50 and trying to read the configuration register.
In every condition, I check the DOUT/RDY pin to be low before starting to write.
The board wire connections make available to the AD7190 this signal levels:
AIN1 short circuited with AIN2 (with this condition I should have 0x800000 on Data Register -> never had)
Thank you in advance for your cooperation,