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AD9361 RX Path

Question asked by batraaman on Dec 8, 2015
Latest reply on Dec 18, 2015 by DragosB

ADC: 245.76

Data Rate : 30.72 Mhz(I Data + Q Data= 61.44 Mhz)Hello,

We use AD-FMCOMMS2-EBZ  AD9361 RF hardware evaluation board along with Altera SoCKit Cyclone V. We control AD9361 from PC. PC sends AD9361 register read/write commands  through Altera Sockit Cyclone V. This board parses those commands and forwards them to AD9361 using SPI lines.

 

We successfully set up BBPLL, RFPLL Synthesizers, Digital Data Interface, TX Baseband Filter Tuning, TX Secondary Filter Calibration, TX Attenuation, Tx Quadrature Calibration.

We set BBPLL frequency to 983.04 MHz and set BBPLL DIV of 2 – results in a divide by 4. This results in a 245.76 sample clock. The data rate  input to FIR filter is 61.44 Mhz(I data: 30.72msps and for Q data: 30.72msps) and given an interpolation of  2 to HB1 and HB2 (HB3 has been bypassed). The clock frequency we are using is 2.4 Ghz. Transmitting side works fine according to the spectrum waveform on Spectrum Analyzer.

We have issues with receiving side and in the text bellow we will try to describe consequences. We have connected directly the TX2  of our transmitting AD9361  to other AD9361 at RX2 through cable and by providing -10db attenuation in between.


The receiving side AD9361 is working in TDD mode and we have also written the coefficient of RX FIR. Here we are using same configuration as of TX side which are given below.

Interpolation of RX FIR, HB1 and HB2 by 2 (HB3 bypassed)


Unfortunately, we are not able to receive any data. We are using Logic signal tap analyzer in quartus 13.1. The recieve  data is 00h. We have also tried to capture data in time domain from AD9361 board but it is still the same.


Our interface between AD9361 and Altera SoCKit Cyclone V  is working fine. So can you please suggest us that what could be wrong and how to receive at least some data?


Any help would be most welcome.


Aman Batra

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