I am using ZC706 FPGA with AD6676-EBZ.
I downloaded HDL PROJECT -> hdl_2015_r1 that requires Vivado214.4.1 with SW source --> no-OS-2015_R1 that should be compatible?
When I tested the project using SDK, I found an error in ad6676_ebz.c file on line 44 at function jesd204b_gt_clk_enable(JESD204B_GT_RX);
It has missing an argument "lane", hence I set it to 0 and then 1. I am not sure what should be the value of this argument.
The console output for both value is attached. It says pll unlock that is not clear?
Actually, I do not have license for Vivado 2015.2.1 hence I am obliged to use the project for Vivado2014.4.1 but I am not sure which noOS version is compatible with which HDL version. Please let me know.
Moreover, I am not sure how to make it sure that ADC is working fine because I am using a capture.tcl (attached) for capturing the samples in DDR3 and bring it back to PC as a rx.csv file. But it seems it is not working because samples do not change with the adc test pattern they remain similar (see the matlab snapshot). (I already reported this issue at the forum). And, iio scope windows crashes when detect.
Hence, at this point, I do not find any other way to verify the ADC6676 that it is working fine.
Actually, I need a working reference so that I can port that code to a customized FPGA.
Thanks in advance.