This is not the first PLL I design, neither the first ADF4xxx I'm using but here I'm stuck with a problem I do not achieve to understand and I come here to ask for advices. I may possibly do something incredibly stupid that do not appears as it to me !
I've designed a 12 GHz and a 10.7 GHz PLLs using ADF4107 and VCO+prescaler HMC513 and HMC515. I'm using the divide-by-4 output of the VCOs for RF feedback.
PCB is 4-layers rogers RO4350 with coplanar lines for RF paths.
I've implemented both passive and active loop filter with 0 ohms resistor selection as the 10.7 MHz can run with VCO Vtune below 5 V, but the 12 GHz requires higher voltage and so the active filter. the correct bit for POLARITY is set accordingly
Power supplies are very clean, using DC/DC preregulator in shielded box + linear regulator ADP7104 + active filters for voltages above 3V and the 3VD and 3VA are ADP151. The noise levels are at the noise floor of my HP35670a analyzer. Only 50 Hz and harmonics can be seen with quite high level.
REFin is an HP RF generator + a 30dBm max amplifier. I can change then easily the REFin frequency and amplitude. Actually once the level is high enough, there is no impact on the PLL output phase noise if I increase the level up to VDD.
The problem is that it doesn lock everywhere in frequency and when it locks, the phase noise is howful or the carrier is unstable (like FM modulated or close to oscillate). Here under are some phase noise plots :
the blue curve is my last 3 GHz PLL design that we don't care for now, the pink plot is using passive LP on a given frequency where I get something close to the simulation, and the green is on an other frequency.... Active filter is a bit worst in term of locking but almost the same for phase noise.
When it doesn't lock, it can be around an other frequency than the expected one or oscillating over several hundred MHz !
I've tried to change PFD frequency from 10 kHz to 200 MHz. Some combination of VCO frequency / PFD were better (like the pink plot) enabling to lock, some others just not working at all (unlock, or locked with huge oscillation, or howfull close-in phase noise more than 40-50 dB above expectations.
I've set MUXOUT to R_DIVIDER and N_DIVIDER outputs to see if PFD frequencies were correct but I measure 30ms spaced pulses modulated by the correct PFD frequency.... Datasheet is giving no detail here, but I was expecting steady PFD frequency output there. Meanwhile, LOCK DETECT is normally high even with this pulsed PFD outputs on MUXOUT and on the spectrum, one could see that the PLL is unstable anyway (locked in frequency, but like modulated).
Measuring accurately the spectrum around the carrier I could see 82 Hz spaced spurs all around the carrier that nothing in my design seems to generate. Again, power supplies are particularly clean. The wideband noise is ok, this is actually within my loop filter bandwidth that the problems arise...
PLL programming from power boot after a second of delay is achieved like this :
/*******************/ /* Program the PLL */ /*******************/ /* Set Initialisation Register */ u8Status = SetInitialisationRegister (u8PLLNumber, stPLLSettings.u8Prescaler, PD2_ASYN, CP_5_1K_5_0_MA, TC_3_PFD_CYCLES, FASTLOCK_DISABLED, CP_OUTPUT, PD_NEGATIVE, MUXOUT_N_DIVIDER_OUTPUT, PD1_NORMAL, COUNTERS_NORESET ); if (u8Status == ERROR) return ERROR; /* Set Function Register */ u8Status = SetFunctionRegister (u8PLLNumber, stPLLSettings.u8Prescaler, PD2_ASYN, CP_5_1K_5_0_MA, TC_3_PFD_CYCLES, FASTLOCK_DISABLED, CP_OUTPUT, PD_NEGATIVE, MUXOUT_N_DIVIDER_OUTPUT, PD1_NORMAL, COUNTERS_NORESET ); if (u8Status == ERROR) return ERROR; /* Set Reference Register */ u8Status = SetReferenceRegister (u8PLLNumber, u16ReferenceWord, ANTIBACKLASH_2_9_NS, LDP_THREE_CYCLES ); if (u8Status == ERROR) return ERROR; /* Set N Counter Register */ u8Status = SetNCounterRegister (u8PLLNumber, stPLLSettings.u16BCounter, stPLLSettings.u8ACounter, CP_CURRENT_SETTING1); if (u8Status == ERROR) return ERROR;
The registers are correctly sent to the PLL on the SPI line. timings are ok.
Prescaler register is computed by my code to never exceed 300 MHz PFD frequency and has been checked to be correct R, B and A registers are as well computed by my code from PLL parameters : Frequency and PFD value. and have been manually checked as well
For 10.7 GHz (with the VCO divided-by-4 output), the PLL should lock on 2675 MHz using P prescaler -by-16.
My questions are :
1. could anyone confirm that the R and N_DIVIDER outputs on MUXOUT are supposed to be steady periodic signals and not pulsed signals. By the way the pulses are not like digital ones, but exponential increase from 0 to 3V and then sharp fall to 0 during maybe 5 ms and every 30 ms. No capture of this for now but I can make one.
2. Measuring the level with spectrum analyzer at PLL RFin while everything is connected so of course bad return losses, gives a level very low in the range of -15dBm whereas with the amplifier I'm expecting something above 0dBm. Could such PLL behavior be from a lack in RFin level ? Why then LOCK DETECT would show a LOCK if actually the PLL is unstable ?
Any other clue on how to investigate or idea of things to check are very welcome.
Thanks & cheers