AnsweredAssumed Answered

FMCOMMS2 HDL ref design - give FIFO time to fill

Question asked by Orangelynx on Dec 7, 2015
Latest reply on Dec 9, 2015 by Orangelynx



I have been working with the FMCOMMS2 HDL reference design for some time now and want to send custom data. I therefore added a FIFO generator to the Block Design and configured it properly (as suggested in the wiki).


Looking at the ILA readouts, I noticed that the FIFO is always "almost empty". i.e. the empty flag is high 50% of the time. This suggests that the read / write rates are roughly the same, but because the FIFO started out empty, it is always "with its back against the wall".


Obviously the idea of a FIFO is to always operate somewhere in the middle of the stack, but I cannot get there because I cannot tell the AD9361 to wait with reading until the FIFO is initially half full, can I?


So I was just wondering if anyone has ever encountered a similar issue and how they resolved it.