We are working on a project in which we are using the acquisition board AD-FMCADC2-EBZ coupled with the Xilinx ZC706 evaluation board. We took the HDL reference code provided by Analog Devices to work on it - specifically the project fmcadc2_zc706 for Vivado 2014.4.1.
Our goal is to take the bits captured by the ADC and process it with our own code - that would be inserted in the reference code mentioned above. We are going to read the data coming out from the ADC, process it, and produce our desired bits. These bits will be then stored in the ARM's memory and sent to an external PC by Ethernet.
Our processing of the bits is very simple: It will do the moving average of each 4 samples and compare it with the current bit. For each sample, our code generates one output bit which will be grouped into 8, and then stored on the ARM’s memory or simply sent by the Ethernet output - we are going to work with an effective rate of 125MB/s (1GS/s / 8).
We have no problem by generating an output of 32 or 64 bits to interface with the DMA.
The image below shows a part of the block diagram in which we want to insert our code:
We are going to use the adc_clk and adc_wr signals to synchronize it with our clock.
Is it possible to implement that (knowing the speed we want to reach)? Furthermore, we would like to know where is the best part of the reference code in which we can insert our code (between one of the two parts indicated by the green arrows in the figure). There is a better way to do what we need?
Finally, there are two outputs for the axi_adcfifo: one that interfaces the DDR3 and another the DMA for the ARM SDRAM. Is it necessary to use the DDR3 interface?