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customising fmcomms 4 hdl design data reception problem

Question asked by rahulram on Dec 7, 2015
Latest reply on Dec 11, 2015 by DragosB

hi,

    i know i have been posting on this problem for quite a bit but the problem is that i am still not able to fully realise my design , so pls help me. i will try to explain clearly , i am using fmcomms 4 board along with zc706 board with no os driver provided for it. now i have read how to modify the design to send data through our custom ip in the form of a fifo. i have been successful in sending data and receiving the data through a custom fifo which is directly connected to the ad9361  without (axi_dac_dma and axi_adc_dma). i store the data i and q in the fifo and send it directly to ad9361 pins on i and q and receive the data on adc_i0 and adc_q0 pins of ad9361 . i am able to decode this data properly on the receiver side. now when i remove the fifo and replace it with my custom block which is generating the same i and q data in the same format , my data on the receiver side is not decoding as i dont get the same data i was sending through fifo. the sent data  is matching exactly in fifo as well as my custom ip(i.e i and q data i send from both the blocks),but on the receiving side the data changes in amplitude and is saturating  . can anyone expalin me why this is happening? .pls help me .if needed i can give more information.thank you

 

regards

 

rahul

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