I am using a customize FPGA platform with AD6676-EBZ Vivado2014.4.1, NoOS Rev no-OS-2015_R2.
I want to use VIO/chipscope scope for plotting an eye diagram for the data comes through the ADC test pattern in FPGA.
I have found that your IP JESD_GT has a 2D eye scan logic that provides eye scan information to microblaze over axi4 bus.
Actually, I want to plot an eye scan in hardware manager over jtag.
Is there anyway to do a serial i/o scan in hardware manager with the given 2D eye scan logic?
Please let me know.