Hello, I'm using HMC703 to generate 1.6GHz clock from a 100MHz source. In ADIsimPLL I chose the PLL to be an interger-N PLL and typed in the frequencies needed (see pictures attached). However the software says the HMC703 is not compatible with the requirement, as the N-divider is 8 (which is apparently 16 in my case). Does anyone got this problem before, and how can I fix it? Thank you!
UPDATE1: My ADIsimPLL version is 4.00.04
UPDATE1: I tried another design with same frequency requirement, this time with HMC832 and the software works fine. The N-division factor is 16 as shown in the Chip Programming Assistant window. So I suppose this is a software bug specific to HMC703.