I´m currently developing an audio DAC device with an AD1896 ASRC to reduce bitrate abd jitter.
The input data (SCLK_IN, LRCLK_IN, SDATA_IN) comes from a CS8416 SPDIF digital reciever and looks like correct. The parameters of input data are given below:
- SCLK_IN = 2.8224 MHz,
- LRCLK_IN = 44.1 kHz,
- SDATA_IN = I2S, 24 bit.
The AD1896 is configured as show below:
- MMODE[2:0] = 000 - both serial ports are in slave mode;
- SMODE_IN[2:0] = 001 - input port mode = I2S;
- SMODE_OUT[1:0] = 01 - output port mode = I2S;
- WLNGTH_OUT[1:0] = 11 - output port bitrate = 16bit.
The AD1896 is clocked by 22.5792 MHz quartz oscillator. The SCLK_OUT and LRCLK_OUT are receiving from FPGA and looks like correct, too: SCLK_OUT = 2.8224 MHz, LRCLK_OUT = 44.1 kHz.
So, I expect to receive a valide data on SDATA_OUT pin, but it isn't.
I can send good I2S,24bit data on SDATA_IN pin, or I deassert SDATA_IN to GND - it does not matter: the data on SDATA_OUT pin look like identically bad.
So, can somebody help me to find out why the AD1896 isn`t working?
Thank you in advance!