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Phase Truncation Spurious calculation in AD9910

Question asked by bibi242 on Dec 4, 2015
Latest reply on Dec 9, 2015 by bibi242

Hello All

I have doubt regarding phase truncation error spurious calculation in AD9910

when I set Fclk=1GHz& FTW=1 (fout=0.23283064365Hz)

ADI Sim DDS predicts phase truncation error component at 1.525879E+4Hz


But by calculation it should be at

Fo= ETW*Fclk/2^B

here B=13 (since phase accumulator truncated from 32 bits into 19)

So error will repeat periodically after 2^13 fclks.

So fundamental component in truncation error is calculated by


but its matching when I take B=16


Please give me some advice on this