I am working on a FIFO-based interface to the AD9361 DAC block using the dev branch of the HDL reference design (because I'm using Vivado 2015.2.1)
I can build it fine using Verilog as project language, however I'd rather use VHDL since the rest of my code is written in VHDL and I have some trouble integrating the Verilog wrapper in my project properly.
When setting the project language to VHDL in Vivado, I get some errors when generating the block design, such as:
Unsupported VHDL data type 'INTEGER' for bool value
Failed to convert bool value 'false' to HDL value
Failed to get HDL value for model parameter 'DMA_2D_TRANSFER'
since its just multiple occurences of these errors, I hope someone can help me to get rid of this.
I'm building for ZC706.
I'd appreciate any assistance you can provide