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sampling_freq_tx and sampling_freq_rx relation with adc clock or l_clock

Question asked by rahulram on Dec 4, 2015
Latest reply on Dec 7, 2015 by AdrianC


   i am using fmcomms 4 board along with zc706 with the no os driver provided on site. i have built the reference design in vivado and am using it to send and recieve data from my custom block.i want to send data and recieve it at 44 mhz . my problem is that when i provide clock to my module from zynq i am getting the data partially but am not able to recieve it in full format so i decided to provide clock to my module from ad9361 ie from l_clk. from my previous discussions i have learnt that whatever sampling freq we set in api in main.c we get 2*samp_freq at the l_clk for 1tx 1rx mode . however i learnt that whenever i set 20 mhz i get proper l_clk output of 40 mhz but when i set the samp_freq at 22 mhz i dont get a rate of 44 mhz at l_clk because of which i am not able to provide this clock to my custom block .can u pls tell me why this is happening?and also i believe that while sending data through DAC only the first 12 bits of data is valid and the last 4 bits are ignored so is it that while recieving the data through ADC only the last 12 bits are valid and the first 4 bits are ignored? pls help me with this . thank you