AnsweredAssumed Answered

AD6676EBZ system configuration

Question asked by tuananhdrg on Dec 3, 2015
Latest reply on Feb 1, 2016 by DragosB



I am working on ZC706 with AD6676-EBZ, ref design Vivado 2014.4.1. I am trying to capture the data from DDR3 using adc_capture function given in noOS driver (ad6676_ebz.c). I'm using these two functions:

adc_capture(16384, ADC_DDR_BASEADDR);

Xil_DCacheInvalidateRange(ADC_DDR_BASEADDR, 16384);


I'm not able to capture the correct samples. Even when I change different test patterns the captured data do not change.  In the attached files you see the system configuration. I have a doubt on the parameters, especially the JESD204B and the JESD_gt IPs. I use the default parameters given in the ad6676_ebz.c except this one jesd204b_gt_clk_enable(JESD204B_GT_RX, 1). The default code has an error in this function because there is not the "lane" argument.


I expect that there are two lanes in the JESD link but in the console I see only one link PLL locked. The default reference clock frequency of the AD6676 is 200 MHz so I changed the corresponding parameters in the xdc file. Please let me know if the system is correctly configured. You can find the snapshots of my project on the attached files.




Best Regards.

Tuan Anh