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ADF4159: ramp clock divider issues?

Question asked by atownley on Dec 3, 2015
Latest reply on Dec 18, 2015 by rbrennan



I'm having issues generating a ramp using ADF4159 with a custom VCO. I had first tried using the same VCO, on its own PCB, along with the evaluation board (EV-ADF4159EB3Z), and was able to generate ramps without much issue. For this case, I programmed the part using the provided evaluation board software.


Now, the VCO and ADF4159 are integrated on a new PCB, and I am now programming the part via an FPGA following the procedure in the datasheet (writing registers in order from 7 to 0). I am able to achieve lock across the full frequency range, but when I try to enable ramping, nothing changes (VCO control line is flat).


My first step in debugging was to enable ramp complete to MUXOUT (setting both the relevant R0 and R4 bits). This didn't show anything at the outputs, so I also tried MUXOUT setting 1010 (CLK DIVIDER OUTPUT), which also doesn't seem to produce any output.


Any suggestions for debugging?