I would like to sync the ADP5052 with an external clock provided by an FPGA. The FPGA is to be powered by the ADP5052, so the external clock won't be available until after the first channel comes up. Should the SYNC/MODE pin be pulled high, low, or left floating prior to the start of the external clock? From the datasheet, I see that the part operates in forced PWM mode when SYNC/MODE is pulled high and PWM/PSM mode when pulled low. But the ADP505x Buck Designer suggests that SYNC/MODE be simply connected to the external clock signal.