According to the AD1974 datasheet, it supports an 8kHz sample rate. What are the proper register settings and external MCLK frequency for setting the the ADC?
Supports 24 bits and 8 kHz to 192 kHz sample rates
To run the part at 8 kHz, you must run the part in ‘Direct Lock’ mode. This requires turning off the PLL and using MCLK as the clock source for the ADC. It is also important that the Fs multiplier be set to 512x and therefore an MCLK of 4.096 MHz needs to be provided.
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