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AD9361 Reg Loop back in Verilog HDL directly at I/O for ref design ZC706- FMCOMMS5

Question asked by chiru on Nov 30, 2015
Latest reply on Dec 2, 2015 by CsomI

Ref Design Taken : AD9361 configuration example based on FMCOMMS5 ZC706 zynq platform.

 

Work Done :

 

          1) Verilog Code modified to loop back the RX Channel to Tx Channel 2RX 2TX mode after configuration

 

             of AD9361 from Zynq via SPI interface  (NOT using C function ad9361_bist_loopback and ad9361_hdl_loopback).

 

          2) Directly assigning the RX ports and Clock to TX ports and clocks in verilog at I/O level in system top module

 

Test Setup : Feeding sine tone with 1 Mhz bandwidth @ 2.4GHz to ADC AD9361. Observing loop back in spectrum analyser after up conversion  again to 2.4GHz

 

Problem : We have configured 2 AD9361 chips in above loop back mode. Observation is that only ad9361_1 is working in perfect loopback for both the channels. In ad9361_0 chip only one channel is working fine in loop back mode. Other channel spectrum is not proper.

 

Our Intention : To loop back all the channels in both chips, tap the RX signals of ADC do some processing and loop back the data

 

for upconversion again. Entire design will be developed in verilog HDL

 

 

Kindly help in resolving this.

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