For the SHARC+ cores in the ADSP-SC58x, there is an unexplained special step in the startup code.
./SHARC/lib/src/crt_src/SC5XX_hdr.asm has a "WAIT_LOOP" that depends on bits in RCU0_MSG.
There is corresponding code in adi_code_enable() found in adi_core.h.
The HRM calls these bits "C1ACTIVATE" and "C2ACTIVATE"; regrettably, the source code has hard-coded values (rather than use the BITM_RCU_MSG_C1ACTIVATE and BITM_RCU_MSG_C2ACTIVATE defines in ADSP-SC58x.h).
My question is: what functionality does this serve? What advantage is there to delay the SHARC+ boot until the bit is set?
P.S.: there is a silicon anomaly workaround in adi_code_enable() that refers to 36-10-0005; I'm presuming this is 20000045 in the anomaly document published to those of us outside Analog Devices?
P.P.S.: at the moment, doing a SHARC+ restart with adi_code_enable() is really, really slow (milliseconds) due to the silicon anomaly workaround. Is there any other mechanism to quickly set the SHARC+ program counter to a particular address?