AnsweredAssumed Answered

MEMORY-TO-MEMORY PORT DMA

Question asked by jsksra1 on Nov 30, 2015
Latest reply on Dec 3, 2015 by jsksra1

Hi  ,

 

From the hardware reference of ADSP - 21489

(http://www.analog.com/media/en/dsp-documentation/processor-manuals/ADSP-214xx_hwr_rev1.1.pdf )

It has been mentioned that


"Data throughput for internal to internal transfers is 12 PCLK cycles for 64-bit data."

 

Hence if I want to transfer 1000 samples of data from (suppose) block 2 (pm) to block 3 (dm), it is sopposed to take (1000/2) * 12 cycles = 6000 cycles.

but if I profile it is consuming 12,017 cycles which is double than what we expect.

 

What is the reason for this ??

 

Please find the code snippet, let me know if I am wrong in doing so :

 

 

#define SAMPLES  1000

 

//Sources
*pIIMTMR = (int)&Data_In[0];
*pIMMTMR = 1;
*pCMTMR = SAMPLES;

 

 

//Destination
*pIIMTMW = (int)&Data_Out[0];
*pIMMTMW = 1;
*pCMTMW = SAMPLES;
*pMTMCTL |= MTMFLUSH;
NOP();NOP();NOP();NOP();NOP();NOP();
*pMTMCTL &= ~MTMFLUSH;

 

 

START_CYCLE_COUNT(startCount);
*pMTMCTL |= MTMEN ;

 

 

/* Begin adding your custom code here */
while(*pCMTMR)
{
NOP();
}
STOP_CYCLE_COUNT(stopCount,startCount);
printf("\n%d",stopCount);
*pMTMCTL = 0;

 

Regards

Sravan

Outcomes