I have 2 questions.
I am now using ADC(ADAU1977) and DSP(ADSP21489).
On the ADC, there is a BCLK polarity bit on a ADC control 2 register.
On the SHARC, there is a CKRE bit on SPCTLx register.
Do I have to configure them as the same setting?
In other words, if ADC samples the data on rising edge, SHARC also has to sample the data on rising edge?
There is a SDATA delay bit on the ADC Control 1 Register on ADAU1977.
There is a MFD(Multichannel Frame Delay) on the SPMCTLx register on ADSP21489.
Do they have to be configured to be the same amount of delay setting?