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AD6676 External Clock

Question asked by 0dBc on Nov 28, 2015
Latest reply on Dec 4, 2015 by DragosB

Hi ADI people,

 

We have been trying to get the AD6676 eval board work with an externally applied 3.2 GHz clock. There is already a discussion on the same subject here: https://ez.analog.com/message/201132#201132 but the solution is not posted. We have already wasted a day's work trying to modify the driver but no luck so far. I have tried the following:

 

1) removed the resistors R95 and R100.

2) set adc_oen = 0, adc_sela = 1, adc_selb = 0, adc_s0 = 0, adc_s1=1, adc_resetb = 1;

3) set use_external_clk_enable to 1. this variable is inside the default_init_param struct. But in the driver this variable is not used anywhere else. There must be a mistake.

4) set the CLOCKSYN_ENABLE register (0x2A0) to 0xC0.

5) set the register 0x2A5 to 0x5. This register is named as CLOCKSYN_LOGEN in the driver, but in the datasheet it is named as VCO_CAL_RESET. Which one is correct? Also according to register map given on the page 67 of AD6676 datasheet, last three bits of register 0x2A5 is RESERVED. If the register is RESERVED why are we instructed to write to it on table 28?

 

After doing the stuff above, we executed the driver. Everything seems to be initialized successfull but there is no data coming out of the ADC, i.e. adc_data_a and adc_data_b are all zeros.

 

So what are we doing wrong here?

 

The AD6676 seems like a great product but the documentation about the registers is far below ADI's usual high standards.

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