i am using the fmcomms4 board along with zc706 and am driving it with no-os drivers provided for the reference hdl design.
i have tested the reference examples given on the website and it seems to be working fine . Now i want to customize the reference design so that i only use the ad9361 block from the reference design and am driving the i ( real) and q (imaginary) data directly from my module into the ad9361 and my module recieves the data from adc pins on ad9361 . i have taken care of all the signals required to and am able to send and receive my data from my custom block. Now my problem is that my block may generate data on two different clocks depending on two different mode selections. as far as i know the ad9361 drives data according to the sampling frequency we set in the api functions tx_samp_freq and rx_samp_freq and accordingly the l_clk output of ad9361 is set. my question is that can i set the clock of ad9361 from the hdl design such that the output clock coming out of my custom block can be given as input to the ad9361 such that it drives the data at the desired rate.Next part of my question is that as my transmitter may transmit the data at any of the two rates which i send can i configure the reciever to accept data at any of the two clock rates so that it gets decoded properly. iwant to know what are the functions of pins rx_clk_in_p,rx_clk_in_n,rx_frame_in_p and rx_frame_in_n can i change this pins to drive my clock inside the module ,cause i read somewhere that l_clk is dependent on rx_clk_in.pls help ,thank you.