I have a basic question.
When FMCW ramp is generated through programming PLL synthesizer for N frequency steps, PLL loop bandwidth should be chosen enough small to prevent frequency vs time from appearing like a staircase behavior; otherwise, if PLL loop bandwidth is not enough large, frequency vs time will not follow the desired linear ramp with the desired accuracy.
So it seems that for each ramp time there is an optimum value of PLL bandwidth, and if the ramp time is changed at system design level , the PLL loop filter components have to be changed.
If synthesizer reference is made through a DDS, there is more level of freedom in the choice of PLL loop bandwidth.
Is this correct ? Where can I find some reference or tool for the optimum design of PLL loop bandwidth without DDS?