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Using CLK_OUT from the AD9361 with the AD-FMCOMMS3-EBZ and ZC706

Question asked by 85083074@qq.com on Nov 25, 2015
Latest reply on Nov 26, 2015 by mhennerich
Branched from an earlier discussion

Hi,Lars

     I have some problems ablout CLK_OUT signal . I want to use CLK_OUT as my BBP master clock,so I got the relative pin number H4 accoding to ad-fmcomms2 schematic diagram:

1.jpg

2.jpg

 

 

     Then , I open the ML605_Hardware_User_Guide_ug534  (I use ML605 FPGA ) and find the H4 pin :

It is connected to the A10 in the LPC_FMC.

3.jpg

 

     So I write it to the ucf file :

4.jpg

     I also changed the relative register 0x00A using No-OS :

5.jpg

      I select XTALN(or DCXO) and in default ,it may be 40MHz,is that right?  But when I sample the clk_out with a 200MHz clock,it remains high,and I don't know why. What's wrong?

 

Yours,

Wang

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