I have some problems ablout CLK_OUT signal . I want to use CLK_OUT as my BBP master clock,so I got the relative pin number H4 accoding to ad-fmcomms2 schematic diagram:
Then , I open the ML605_Hardware_User_Guide_ug534 (I use ML605 FPGA ) and find the H4 pin :
It is connected to the A10 in the LPC_FMC.
So I write it to the ucf file :
I also changed the relative register 0x00A using No-OS :
I select XTALN(or DCXO) and in default ,it may be 40MHz,is that right? But when I sample the clk_out with a 200MHz clock,it remains high,and I don't know why. What's wrong?