I am using your evaluation board AD6676-EBZ with my customize FPGA platform having kintex7 on it.
I imported VC707 reference design to it withtout ethernet ip.
For reference I have ZC706 zynq platform.
It seems the reference design is working from SDK console messages.
Now, I would like to plot an eye diagram to evaluate my customize platform.
As, I found there is an eye_scan logic inside the jesd_gt logic in reference design, I would like to know how can I use this logic for eye diagram plot either through jtag in hardware manager (Do I need to use ibert ip for it)? or if there is anyways to use eye_scan scope under linux with petalinux?
Please let me know.