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ADN2915's Output Data Rate

Question asked by Tee on Nov 25, 2015
Latest reply on Feb 29, 2016 by Dongfeng

Hi ADI Folks,

 

I have a query on the ADN2915 output data rate on why it is half of the input when the frequency is above 5.6Gbps.

 

I tried to understand more from the datasheet and below is the extract from the ADN2915's datasheet which seems to be the justification to why the output data rate will be half of the input when the frequency is above 5.6Gbps.

 

 

"The default output clock mode is a double data rate (DDR) clock, where the output clock frequency is ½ the data rate. This allows direct interfacing to FPGAs that support clocking on both rising and falling edges. Setting DDR_DISABLE (OUTPUTA[2]) = 1 in Register 0x1E enables full data rate mode. Full data rate mode is not supported for data rates in the highest octave between 5.6 Gbps and 11.3 Gbps. 

(Reference : ADN2915's Datasheet under Page 29, section "Double Data Rate Mode") "

 

Could you help to confirm my understanding is correct? Thanks.

 

PS: I would appreciate if further information can be shared on why it is not supported above 5.6Gbps, thanks.

 

Best Regards,

Weiren

 

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